C100 978-4-86348-348-4 2013 Symposium on VLSI Circuits Digest of Technical Papers A 10-Bit 800-MHz 19-mW CMOS ADC

Abstract—A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Applying full-rate nonlinearity and gain er-ror calibration, a prototype realized in 65-nm CMOS tech-nology achieves an SNDR of 52.2 dB at an input frequency of 399.2 MHz and an FoM of 53 fJ/conversion-step. The concept of charge steering has been recently revived as a means of achieving low power dissipation at high speeds [5]. While not identified as such, this concept has also been utilized in amplifiers in [6] and [7] but only for linearities of around 6 bits. This paper describes a 10-bit pipelined ADC that employs circuit and architecture techniques to improve the linearity and noise performance of charge-steering op amps while maintain-ing their high power efficiency. Charge-steering Op Amp A conventional two-stage op am