Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers

The rising complexity of verification has led to an increase in the use of FPGA prototyping, which can run at signifi-cantly higher operating frequencies and achieve much higher coverage than logic simulations. However, a key challenge is observability into these devices, which can be solved by em-bedding trace-buffers to record on-chip signal values. Rather than connecting a predetermined subset of circuits signals to dedicated trace-buffer inputs at compile-time, in this work we propose that a virtual overlay network is built to multiplex all on-chip signals to all on-chip trace-buffers. Subsequently, at debug-time, the designer can choose a signal subset for observation. To minimize its overhead, we build this network out of unused routing multiplexers, and by using optimal bipartite graph matching techniques, we show that any sub-set of on-chip signals can be connected to 80–90 % of the maximum trace-buffer capacity in less than 50 seconds