A 10-Bit 1-GHz 33-mW CMOS ADC

Abstract- A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step. This paper describes a pipelined ADC architecture that inherently obviates the need for a high-gain, linear op amp. The ADC instead deals with capacitor mismatches by digital calibration. It also corrects for the gain error of each stage in the digital domain. Architecture The key to easing the op amp linearity requirements is to resolve as many bits as possible in the first stage. This also relaxes the tolerable gain error in subsequent stages. A practical limit arising from kickback noise, powe