Benmao Cheng is a visiting scholar from China. Abstract—This paper proposes a novel asynchronous design template, Blade, that uses single-rail logic, a reconfigurable delay line, and error detecting latches to reliably detect and recover from timing violations due to process variations and delay faults of single event upsets. The template employs a novel speculative handshaking paradigm that improves average-case performance by taking advantage of the fact that errors occur with low probability. We will analytically compares the performance of this template with both traditional synchronous designs and the state-of-the-art synchronous resiliency strategy Bubble Razor. Our results demonstrate the potential benefit of our approach as well as ...
The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS...
Abstract — Nanoelectronic design faces unprecedented relia-bility challenges and must achieve noise ...
ISSN: 0018-9340This paper presents hardening techniques against fault attacks and the practical eval...
2019-02-14As advancements in process technology slow and the ubiquity of mobile and embedded devices...
Abstract—As manufacturing processes continue to shrink and supply voltages drop, timing margins due ...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...
The operating clock frequency is determined by the longest signal propagation delay, setup/hold time...
Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to...
As device scaling continues, process variability and defect densities are becoming increasingly chal...
Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to...
Increasing dynamic variability with technology scaling has made it essential to incorporate large de...
It is getting increasingly difficult to verify processors and guarantee subsequent reliable operatio...
[[abstract]]Delay variation factors are often statistic in nature. Here, we review and compare three...
[[abstract]]©2008 IEEE-Delay variation can cause a design to fail its timing specification. Ernst in...
Asynchronous design has been an active area of research since at least the mid 1950's, but has ...
The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS...
Abstract — Nanoelectronic design faces unprecedented relia-bility challenges and must achieve noise ...
ISSN: 0018-9340This paper presents hardening techniques against fault attacks and the practical eval...
2019-02-14As advancements in process technology slow and the ubiquity of mobile and embedded devices...
Abstract—As manufacturing processes continue to shrink and supply voltages drop, timing margins due ...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...
The operating clock frequency is determined by the longest signal propagation delay, setup/hold time...
Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to...
As device scaling continues, process variability and defect densities are becoming increasingly chal...
Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to...
Increasing dynamic variability with technology scaling has made it essential to incorporate large de...
It is getting increasingly difficult to verify processors and guarantee subsequent reliable operatio...
[[abstract]]Delay variation factors are often statistic in nature. Here, we review and compare three...
[[abstract]]©2008 IEEE-Delay variation can cause a design to fail its timing specification. Ernst in...
Asynchronous design has been an active area of research since at least the mid 1950's, but has ...
The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS...
Abstract — Nanoelectronic design faces unprecedented relia-bility challenges and must achieve noise ...
ISSN: 0018-9340This paper presents hardening techniques against fault attacks and the practical eval...