A Layout Technique for Millimeter-Wave PA Transistors1

Abstract—The distributed interconnect parasitics within large transistors markedly degrade the output power and efficiency at millimeter-wave frequencies. This paper develops a model for such structures and proposes a layout technique to reduce the effect of source terminal parasitics. The technique is applied to a 60-GHz prototype in 65-nm CMOS technology, raising the output power from 5 to 10 dBm and the drain efficiency from 3.7 % to 10.7%. Index Terms—Millimeter-wave power amplifier, layout tech-nique, distributed parasitics, source parasitics, power efficiency. I