Charge Steering: A Low-Power Design Paradigm

Discrete-time charge-steering circuits consume less power than their continuous-time current-steering counterparts even at high speeds. This advantage can be exploited in the design of semi-analog circuits such as latches, demultiplex-ers, and CDR circuits as well as mixed-mode systems such as ADCs. Employing charge steering in 65-nm CMOS technology, a 25-Gb/s CDR/deserializer consumes 5 mW and a 10-bit 800-MHz pipelined ADC draws 19 mW. I