Proteus system architecture and organization

Abstract: The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine, opti-mized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/mnd. The system em-ploys hierarchical reconfigurable interconnection net-work with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for intemal data transfers. The system is designed to use 256 to 1,024 RISC processors. The processors use 1 M byte external R e d w r i t e Allocating Caches for reduced multi-processor contention. The system detects, locates and re-places faulty subsystems using redundant hardware to facilitatefault tolerance. The parallelism is directly con