A Low-Power 60-GHz CMOS Transceiver for WiGig Applications

Abstract—Adirect-conversion transceiver includingbase-band amplifiers and filters employs a 60-GHz quadrature VCO and a feedforward divider with no buffers to achieve a low power consumption. Designed in 40-nmLP CMOS, the radio presents a noise figure of 4.8 to 8.2 dB in the receive mode and an output power of +10 dBm in the transmitmode while drawing 56 mW and 124 mW, respectively. Recent work on 60-GHz radios has demonstrated high levels of integration in CMOS technology [1, 2, 3]. For such radios to find their way into mobile devices, their power consumption must also be reduced while maintaining both a high receive (RX) sensitivity and a high transmit (TX) output power. This paper describes a low-power 60-GHz transceiver for WiGig ap-plications operating with QPSK modulation. Four principles are presented that improve the performance: (1) a “minimal