25.7 A 2.4GHz 4mW Inductorless RF Synthesizer

Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This paper addresses this “last inductor ” problem and proposes an integer-N synthesizer architecture that achieves a phase noise and a figure of merit (FOM) comparable to those of LC-VCO-based realizations. The use of ring oscillators instead of LC implementations offers numerous advantages: smaller area, much less coupling to and from other circuits, a much wider tuning range, straightforward generation of multiple phases, and the ability to multiplex several small rings so as to cover multiple bands with minimal area penalty. However, the far inferior FOM of rings has discouraged their use in RF synthesis. The loop bandwidth of traditional type-II PLLs is bounded by “Gardner’s limit ” to fREF/10, and typically less than fREF/20 to suppress the reference spurs, thus failing to reduce the ring phase noise sufficiently. The PLL architecture introduced here avoids Gardner’s limit, achieving a loop bandwidth of approximately fREF/2, and hence substantial reduction of the VC