Add to ORKGAbstract. VerICS is a tool for the automated verification of timed automata and protocols written in both the Intermediate Language and the specification language Estelle. Recently, the tool has been extended to work with Timed Automata with Discrete Data and with multi-agent systems. This paper presents a prototype Timed Automata with Discrete Data model of Java programs. In addition, we show how to use the model together with the verification core of VerICS to validate the well-known alternating bit protocol written in Java. 1
We introduce a formal framework to provide an efficient event-based monitoring technique, and we des...
We introduce a formal framework to provide an efficient event-based monitoring technique, and we des...
In previous work, we have proposed a model-based approach to developing real-time Java programs from...
Abstract. In the paper we show that automatic verification of Java programs is feasible. In particul...
Abstract. A new approach to verification of timed security protocols is given. The idea consists in ...
MONA implements an efficient decision procedure for the logic WS1S, and has already been applied in ...
Abstract—To effectively cope with correctness issues of concur-rent and timed systems, the use of fo...
Abstract. The aim of this work is to describe the translation from Intermediate Language, one of the...
The paper presents a new tool for automated veri cation of Timed Automata as well as protocols wri...
Given the intractability of exhaustively verifying software, the use of runtime-verification, to ver...
International audienceWe present "Verified JavaBIP", a tool set for the verification of JavaBIP mode...
synchronizers, timed automata, UPPAAL, Java. This paper describes the design and implementation of a...
In the paper we present the current theoretical base of the J2FADD tool, which translates a Java pro...
Many real-time systems are safety- and security-critical systems and, as a result, tools and techniq...
Abstract. The model checking tools Uppaal and VerICS accept a description of a network of Timed Auto...
We introduce a formal framework to provide an efficient event-based monitoring technique, and we des...
We introduce a formal framework to provide an efficient event-based monitoring technique, and we des...
In previous work, we have proposed a model-based approach to developing real-time Java programs from...
Abstract. In the paper we show that automatic verification of Java programs is feasible. In particul...
Abstract. A new approach to verification of timed security protocols is given. The idea consists in ...
MONA implements an efficient decision procedure for the logic WS1S, and has already been applied in ...
Abstract—To effectively cope with correctness issues of concur-rent and timed systems, the use of fo...
Abstract. The aim of this work is to describe the translation from Intermediate Language, one of the...
The paper presents a new tool for automated veri cation of Timed Automata as well as protocols wri...
Given the intractability of exhaustively verifying software, the use of runtime-verification, to ver...
International audienceWe present "Verified JavaBIP", a tool set for the verification of JavaBIP mode...
synchronizers, timed automata, UPPAAL, Java. This paper describes the design and implementation of a...
In the paper we present the current theoretical base of the J2FADD tool, which translates a Java pro...
Many real-time systems are safety- and security-critical systems and, as a result, tools and techniq...
Abstract. The model checking tools Uppaal and VerICS accept a description of a network of Timed Auto...
We introduce a formal framework to provide an efficient event-based monitoring technique, and we des...
We introduce a formal framework to provide an efficient event-based monitoring technique, and we des...
In previous work, we have proposed a model-based approach to developing real-time Java programs from...