Analysis and Modeling of Clock-Jitter Effects in Delta-Sigma Modulators

Random variation in the timing of clock edges (namely, clock-jitter) is a critical problem that is becoming the main limitation in the performance of state-of-the-art data-converters. The problem of clock-jitter is a very critical issue and can significantly deteriorate the achievable signal-to-noise ratio (SNR) of an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) by several dBs. For example, nowadays, the limitation on increasing the ADC performance in terms of SNR and speed is a clock-jitter specification of 0.1 pico-seconds (ps) on the sampling-clock. Given that delta-sigma (ΔƩ) ADCs are attractive candidates for state-of-the-art wideband and high SNR wireless receivers, thus in the process of designing a ΔƩ ADC, it is instructive to have robust models and estimation for the errors caused by clock-jitter. This is critical in extracting the requirements on clock-jitter for a given target performance and also to be able to explore efficient solutions and techniques that can remedy the effects of clock-jitter on the ADC performance. In this context, this chapter is intended to provide a comprehensive background and study for the effects of clock-jitter in the sampling-clocks of ΔƩ modulators. The study includes detailed analysis for the effects of clock-jitter on various waveforms and signals provided by different types of DACs used in ΔƩ modulators. Also, efficient Matlab/Simulink ® models for additive errors induced by clock-jitter in ΔƩ modulators are shown so that to help designers characterize the sensitivities of various types of ΔƩ architectures to clock-jitter. The robustness of the adopted models is demonstrated through illustrative examples based on system-level simulations using Matlab/Simulink