Protecting Caches Against Multi-Bit Errors Using Embedded Erasure Coding

Abstract—Technology scaling advancement coupled with op-erational and environmental effects make embedded memories more vulnerable to both manufacturing and transient errors including multi-bit upsets. Conventional error correcting codes incur high latency, area, and power overheads to correct multi-bit errors. In this paper, we propose embedded erasure coding (EEC), a low-cost technique that can correct multi-bit upsets with low overheads. It employs interleaved parity bits to provide a fast and low-cost multi-bit error detection. Using the erasure coding concept, the error correction is done by reconstructing the contents of the erroneous cache blocks within each cache set. It trades the performance for higher reliability by reserving a part of the cache (e.g. one way) to store the erasure codes. Our simulation results show that EEC provides high reliability (100% error detection and correction) with a faster error recovery with lower area overhead and less than 3 % performance loss as compared to other state-of-the-art techniques. I