Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation

As DRAM scaling becomes more challenging and its energy ef-ficiency receives a growing concern for data center operation, an alternative approach — stacking DRAM die with thru-silicon vias (TSV) using 3-D integration technology is being undertaken by in-dustry to address these looming issues. Furthermore, 3-D tech-nology also enables heterogeneous die stacking within one DRAM package. In this paper, we study how to design such a heteroge-neous DRAM chip for improving both performance and energy ef-ficiency, in particular, we propose a novel floorplan and several ar-chitectural techniques to fully exploit the benefits of 3-D die stack-ing technology when integrating an SRAM row cache into a DRAM chip. Our multi-core simulation results show that, by tightly inte-grating a small row cache with its corresponding DRAM array, we can improve performance by 30 % while saving dynamic energy by 31 % for memory intensive applications. 1