Hotspots Elimination and Temperature Flattening in VLSI Circuits

Abstract — This paper proposes a new solution to the problem of eliminating hotspots from gate-level netlits as well as examines the effects of timing constraints on the temperature reduction and the overall temperature flattening on the chip. Our core technique consists of three steps. First, a thermal analysis is carried out for logic netlists. (The netlists are assumed to be either isolated or embedded in a larger system with macro-cells.) We then apply a new technique, called isothermal logic partitioning technique (LP-temp), to the netlists, which essentially builds isothermal logic clusters for the netlists and splits each of the logic clusters exceeding the maximum allowed temperature through its hottest point. This will enlarge a contact point for the hotspot to cool down. Finally, the entire system is replaced using a custom designed temperature-aware floorplanner so that the temperature across the entire system is reduced and flattened