Active Pixel Sensor Arrays in 90/65nm CMOS-Technologies with vertically stacked photodiodes

competitive with commercial sensors in conventional technologies. New pixel configurations with stacked photodiodes and high fill factor have been evaluated. Image sensors in deep-submicron can take full advantage of the technology shrink for digital image restoration, balancing remaining technological deficiencies and offering additional processing capabilities. Today’s CMOS sensors are chiefly fabricated in 0.25µm CMOS technology and incorporate a custom DSP for image enhancements [1]. This work is focusing on evaluation of 90/65nm CMOS technology for active photosensor arrays and analog/mixed signal readout circuits. To compensate for the expected larger insufficiencies of the analog sensor array, advantage can be taken of the shrinking potential of further sub-100nm CMOS technologies to implement image enhancement techniques by digital post processing [2, 3]. Application is aimed at embedded imagers for digital cameras in handhelds and alike, using standard digital processes for Systems on Chip. As far as the authors are aware, this is the first study of pixel sensors in sub-100nm CMOS technologies. Two active pixel arrays have been fabricated in 90nm and 65nm CMOS process respectively with 6+1 layer metal stack and copper interconnects (Figure 6). The first chip serves for pixel evaluation and contains a total of 21 pixel arrays with different photo diode and reset configurations. Pixel size is 6x6µ