AND THEN EXPLORES THE LOGICAL AND PHYSICAL IMPLICATIONS OF LEVERAGING THIS TECHNOLOGY IN PROCESSOR-TO-MEMORY NETWORKS.

......Modern embedded, server, graph-ics, and network processors already include tens to hundreds of cores on a single die, and this number will continue to increase over the next decade. Corresponding increases in main memory bandwidth are also required, however, if the greater core count is to result in improved application performance. Projected enhancements of existing electrical DRAM interfaces are not expected to supply sufficient bandwidth with reasonable power consumption and packaging cost. To meet this many-core memory bandwidth challenge, we are com-bining monolithic CMOS silicon photonic