POWER AWARE TEST-DATA COMPRESSION FOR SCAN-BASED TESTING

In this paper a new approach that targets the reduction of both the test-data volume and the scan-power dissipation during testing of a digital system's cores is proposed. For achieving the two aforementioned goals, a novel algo-rithm that inserts some inverters in the scan chain(s) of the core under test (CUT) is presented. However, no per-formance or area penalty is imposed on the CUT since, instead of additional inverters, the negated outputs of the scan flip-flops can be utilized. The proposed algorithm targets the maximization of run-lengths of zeros (or ones) in the test set accompanying the CUT. This algorithm combined with the Minimum Transition Count mapping of don't cares in a test set as well as with the alternating run-length code that have been recently proposed, achieves better test-data compression and reduced scan-power results than the relative works in the literature. 1