Add to ORKGAlong with the fast development of dual threshold voltage (dual-Vt) technology, it is possible to use it to reduce static power in low-voltage high-performance circuits. In this paper we present a new signal-path level circuit model and an algorithm based on the new circuit model which introduces the concept of extracting sub-circuits. Experimental results show that, for the ISCAS85 benchmark circuits, our algorithm produces a significant leakage-power reduction similar to the transistor level dual-Vt assignment, but the computational cost is comparative to gate level dual-Vt assignment. 1
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major desig...
A novel technique for incorporating the use of dual supply voltages for low power without performanc...
In this paper we have addressed the problem of realizing dual-VT CMOS circuits for battery-operated ...
Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, ...
The need for low power dissipation in portable computing and wireless communication systems is makin...
Leakage power has become one of the most critical design con-cerns for the system-level chip designe...
In this paper we present efficient procedures for delay constrained minimization of the power due to...
In today’s sub-100nm CMOS technologies, leakage current has become an important part of the total po...
Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption...
This paper introduces a framework for the minimization of leakage power consumption of asynchronous ...
Among several metrics for system performance, power consumption has become a major criterion. As vol...
We propose a new method that uses a combined approach of sleep-state assignment and threshold voltag...
[[abstract]]We study the reduction of static power consumption by dual threshold voltage assignment....
Abstract—We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digi...
Design methodology for dual-VTH scheme using commercially available tools is presented and optimizat...
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major desig...
A novel technique for incorporating the use of dual supply voltages for low power without performanc...
In this paper we have addressed the problem of realizing dual-VT CMOS circuits for battery-operated ...
Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, ...
The need for low power dissipation in portable computing and wireless communication systems is makin...
Leakage power has become one of the most critical design con-cerns for the system-level chip designe...
In this paper we present efficient procedures for delay constrained minimization of the power due to...
In today’s sub-100nm CMOS technologies, leakage current has become an important part of the total po...
Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption...
This paper introduces a framework for the minimization of leakage power consumption of asynchronous ...
Among several metrics for system performance, power consumption has become a major criterion. As vol...
We propose a new method that uses a combined approach of sleep-state assignment and threshold voltag...
[[abstract]]We study the reduction of static power consumption by dual threshold voltage assignment....
Abstract—We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digi...
Design methodology for dual-VTH scheme using commercially available tools is presented and optimizat...
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major desig...
A novel technique for incorporating the use of dual supply voltages for low power without performanc...
In this paper we have addressed the problem of realizing dual-VT CMOS circuits for battery-operated ...