– Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL): Category 2 – AUGMENTING FPGAS WITH EMBEDDED NETWORKS-ON-CHIP

FPGAs are increasing in capacity, allowing the implementa-tion of ever-larger systems with correspondingly increasing bandwidth demands. Additionally, modern FPGAs are be-coming a heterogeneous platform that includes many fast ded-icated blocks such as processor cores, and high-speed I/Os such as DDR3 memory and PCIe. It is becoming a challenge to connect systems in these large heterogeneous FPGAs using the existing low-level interconnect that consists of wires and programmable multiplexers. We propose embedding a high-bandwidth network on-chip (NoC) on future FPGAs to trans-port data in large systems. Two embedded NoC types offer different tradeoffs; mixed NoCs – that use embedded “hard” routers and programmable “soft ” links – have a configurable topology, while hard NoCs – that consist of both hard routers and hard links – are more efficient and faster. Both mixed and hard NoCs demonstrate a significant advantage in both effi-ciency and performance over soft NoCs that are traditionally implemented on FPGAs; 20-23 × smaller, 5-6 × faster and 9-11 × lower power. This work summarizes our previous find-ings that appeared in FPT 2012 and FPL 2013 [1, 2]. 1