Add to ORKGIn scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits ’ reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS’89 benchmark circuits show the effectiveness of the proposed technique. 1
Test power has been turned to a bottleneck for test considerations as the excessive power dissipatio...
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessiv...
During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity...
Abstract- Power consumption in scan-based testing is a major concern nowadays. In this paper, we pre...
[[abstract]]Recently, power dissipation in full-scan testing has brought a great challenge for test ...
Excessive power dissipation can cause high voltage droop on the power grid, leading to timing failur...
Low power design techniques have been employed for more than two decades, however an emerging proble...
[[abstract]]ATPG-based technique for reducing shift and capture power during scan testing is present...
Research on low-power scan testing has been focused on the shift mode, with little consideration giv...
[[abstract]]A scheme that ATPG-based technique for reducing shift and capture power during scan test...
Research on low-power scan testing has been focused on the shift mode, with little or no considerati...
This paper shows that not every scan cell contributes equally to the power consumption during scan b...
Excessive power consumption during test application time has severely negative effects on chip relia...
Excessive power consumption during test application time has severely negative effects on chip relia...
Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquit...
Test power has been turned to a bottleneck for test considerations as the excessive power dissipatio...
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessiv...
During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity...
Abstract- Power consumption in scan-based testing is a major concern nowadays. In this paper, we pre...
[[abstract]]Recently, power dissipation in full-scan testing has brought a great challenge for test ...
Excessive power dissipation can cause high voltage droop on the power grid, leading to timing failur...
Low power design techniques have been employed for more than two decades, however an emerging proble...
[[abstract]]ATPG-based technique for reducing shift and capture power during scan testing is present...
Research on low-power scan testing has been focused on the shift mode, with little consideration giv...
[[abstract]]A scheme that ATPG-based technique for reducing shift and capture power during scan test...
Research on low-power scan testing has been focused on the shift mode, with little or no considerati...
This paper shows that not every scan cell contributes equally to the power consumption during scan b...
Excessive power consumption during test application time has severely negative effects on chip relia...
Excessive power consumption during test application time has severely negative effects on chip relia...
Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquit...
Test power has been turned to a bottleneck for test considerations as the excessive power dissipatio...
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessiv...
During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity...