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Abstract-This paper introduces a novel switch approach for redundant capacitive DACs of a 2b-per-cycle SAR ADC. By using the proposed multi-merged switching algorithm, the conventional trial-and-error search procedure is prevented, which leads to significant switching energy and DAC settling time reductions. The conversion power and speed analysis are presented, which is also verified in behavior simulations of a 6-bit 2b/cycle SAR ADC. The simulation results show that the proposed method can achieve about 37 % power saving as compared to the conventional one. I
In this paper, the design of a 6-bits successive approximation register (SAR) analog to digital conv...
The demands for data converters have soared in the last decade with the boom in consumer electronics...
Abstract − The project presents a 10-bit successive approximation-register analog-to-digital convert...
Abstract—The early reset merged capacitor switching algorithm (EMCS) is proposed as an energy reduci...
Abstract—This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR A...
Abstract — A new method for switching the capacitors in the DAC capacitor array of a successive appr...
Abstract—A novel switching method is proposed and implemented in a 10-bit fully differential SAR ADC...
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs us...
In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy c...
An energy-efficient capacitive digital-to-analog converter (C-DAC) switching with spread second capa...
The digital-to-analog converter (DAC) in SAR anolog-to-digital converters (ADCs) is often dominant f...
A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) usin...
Abstract—Analysis and experimental results for a new switching scheme and topology for charge sharin...
This paper proposes a new method for switching the capacitors in the DAC capacitor array of a succes...
A novel low-energy tri-level switching scheme for low-power successive approximation register (SAR)...
In this paper, the design of a 6-bits successive approximation register (SAR) analog to digital conv...
The demands for data converters have soared in the last decade with the boom in consumer electronics...
Abstract − The project presents a 10-bit successive approximation-register analog-to-digital convert...
Abstract—The early reset merged capacitor switching algorithm (EMCS) is proposed as an energy reduci...
Abstract—This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR A...
Abstract — A new method for switching the capacitors in the DAC capacitor array of a successive appr...
Abstract—A novel switching method is proposed and implemented in a 10-bit fully differential SAR ADC...
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs us...
In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy c...
An energy-efficient capacitive digital-to-analog converter (C-DAC) switching with spread second capa...
The digital-to-analog converter (DAC) in SAR anolog-to-digital converters (ADCs) is often dominant f...
A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) usin...
Abstract—Analysis and experimental results for a new switching scheme and topology for charge sharin...
This paper proposes a new method for switching the capacitors in the DAC capacitor array of a succes...
A novel low-energy tri-level switching scheme for low-power successive approximation register (SAR)...
In this paper, the design of a 6-bits successive approximation register (SAR) analog to digital conv...
The demands for data converters have soared in the last decade with the boom in consumer electronics...
Abstract − The project presents a 10-bit successive approximation-register analog-to-digital convert...
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