Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

sors (TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry can affect the performance of applications differently. Based on the above observation, we firstly formalize the variation-aware scheduling in TLR-CMP as a 0-1 programming problem, to maximize the system weighted throughput. An efficient scheduling algorithm, named IntraVarF&AppSen, is then pro-posed to tackle this problem, which can be proved to be optimal when the number of applications to be scheduled is equal to the number of core pairs. Simulation on a 64-core CMP shows 2.8%-4 % improvement in weighted throughput when compared to prior VarF&AppIPC algorithm. Keywords-process variation; thread-level redundancy; chip multiprocessor; scheduling; I