Profileguided microarchitectural floorplanning for deep submicron processor design

Abstract—As very large scale integration (VLSI) process tech-nology migrates to nanoscale with a feature size of less than 100 nm, global wire delay is becoming a major hindrance in keeping the latency of intrachip communication within a sin-gle cycle, thus substantially decaying performance scalability. In addition, an effective microarchitectural floor planning algorithm can no longer ignore the dynamic communication patterns of applications. This article, using the profile information acquired at the microarchitecture level, proposes a “profile-guided microar-chitectural floor planner ” that considers both the impact of wire delay and the architectural behavior, namely, the intermodule communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on the simulation results here, the proposed profile-guided method shows a 5%–40 % average instructions per cycle (IPC) improvement when the clock frequency is fixed. From the perspective of instruc-tion throughput in billion instructions per second (BIPS), the floor planner is much more scalable than the conventional wirelength-based floor planner. Index Terms—Floor planning, microarchitectural design. I