A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-efficiency While Preserving Responsiveness

Computing workloads often contain a mix of interac-tive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, in-teractive and batch applications are often run on disjoint sets of resources, but this incurs additional energy, power, and capital costs. In this paper, we evaluate the poten-tial of hardware cache partitioning mechanisms and policies to improve efficiency by allowing background applications to run simultaneously with interactive foreground applica-tions, while avoiding degradation in interactive responsive-ness. We evaluate these tradeoffs using commercial x86 multicore hardware that supports cache partitioning, and find that real hardware measurements with full applications provide different observations than past simulation-based evaluations. Co-scheduling applications without LLC par-titioning leads to a 10 % energy improvement and average throughput improvement of 54 % compared to running tasks separately, but can result in foreground performance degra-dation of up to 34 % with an average of 6%. With optimal static LLC partitioning, the average energy improvement in-creases to 12 % and the average throughput improvement to 60%, while the worst case slowdown is reduced noticeably to 7 % with an average slowdown of only 2%. We also evaluate a practical low-overhead dynamic algorithm to control par-tition sizes, and are able to realize the potential performance guarantees of the optimal static approach, while increasing background throughput by an additional 19%. 1