Memory Controller Methodology

Devise different DRAM architecture solutions using 3D-Integration technology for improved bandwidth and evaluate the real-time performance in terms of memory efficiency and bandwidth. Proposed architecture We consider a Parallel-Access (PA) method in which each bank of the DRAM has its own command and data interface to the memory controller. This approach is about using the 3D-Integration technology enabler to make banks into independent memories by removing shared logic meant to reduce the number of pins. This increases the provided bandwidth