Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation

Abstract—This paper proposes a new fault tolerant cache organ-ization capable of dynamically mapping the in-use defective loca-tions in a processor cache to an auxiliary parallel memory, creating a defect-free view of the cache for the processor. While voltage scaling has a super-linear effect on reducing power, it exponentially increases the defect rate in memory. The ability of the proposed cache organization to tolerate a large number of defects makes it a perfect candidate for voltage-scalable architectures, especially in smaller geometries where manufacturing induced process varia-tion (MIPV) is expected to rapidly increase. The introduced fault tolerant architecture consumes little energy and area overhead, but enables the system to operate correctly and boosts the system per-formance close to a defect-free system. Power savings of over 40% is reported on standard benchmarks while the performance degra-dation is maintained below 1%. Index Terms—Cache, fault tolerance, low power, process varia-tion, SRAM, voltage scaling. I