Thermal Feasibility of Die-Stacked Processing in Memory

Processing in memory (PIM) implemented via 3D die stack-ing has been recently proposed to reduce the widening gap between processor and memory performance. By moving com-putation that demands high memory bandwidth to the base logic die of a 3D memory stack, PIM promises significant improvements in energy efficiency. However, the vision of PIM implemented via 3D die stacking could potentially be derailed if the processor(s) raise the stack’s temperature to unaccept-able levels. In this paper, we study the thermal constraints for PIM across different processor organizations and cool-ing solutions and show the range of designs that are viable under different conditions. We also demonstrate that PIM is feasible even with low-end, fanless cooling solutions. We believe these results help alleviate PIM thermal feasibility con-cerns and identify viable design points, thereby encouraging further exploration and research in novel PIM architectures, technologies, and use cases. 1