On the FPGA Dynamic Partial Reconfiguration Interference on Real-Time Systems

Abstract—This work proposes a deterministic hardware and software reconfiguration scheme capable of mitigating interfer-ence on reconfiguration execution time generated by system components performing I/O operations. The scheme decomposes the reconfiguration process into small steps such that it is preemptable, transparent, dynamic and compliant with real-time requirements. Moreover, the impact of the interference on system reconfiguration time was modeled and analyzed. Results show that using the Xilinx Zynq-7000 platform employing an ARM Cortex-A9 processor the reconfiguration time can grow up to 92% when real-time threads are performing I/O operations during hardware reconfiguration. Keywords—Dynamic partial reconfiguration, Real-Time, Field-programmable gate arrays (FPGAs), System-level design, HW/S