This paper presents a high quality H.265/HEVC motion estimation implementation with the cooperation of CPU and GPU. The data dependency from MVP (Motion Vector Predictor) restricts the degree of parallelism on GPU. To overcome the constraint from MVP, we propose to use an estimated MVP on GPU and the accurate MVP to refine the motion vector on CPU. GPU fully utilizes its tremendous parallel computing ability without the restriction from MVP. CPU makes up for the deviation from GPU with a small range refinement. Encoding speed benefits from the high degree of parallelism and compression performance is maintained by the CPU refinement. Experimental result shows that the speedup achieves 2.39 times and 32.77 times in the whole x265 encoder wit...
H.264/AVC is the latest standard for video compression and is a significant advance, but at the expe...
Heterogeneous systems on a single chip composed of CPU, Graphical Processing Unit (GPU), and Field P...
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that...
In the high efficiency video coding (HEVC) encoder, motion estimation (ME) takes up more than 50% en...
This paper provides a multiple-layer parallel motion estimation (ME) scheme implemented on GPU for H...
We propose a highly parallel and scalable motion estimation algorithm, named multilevel resolution m...
The new High Efficiency Video Coding (HEVC) standard will most likely be used in many applications i...
The high computational cost of the motion estimation module in the new HEVC standard raises the need...
Parallel processors such as Graphics processing units (GPUs) have emerged as co-processing units for...
Parallel processors such as Graphics processing units (GPUs) have emerged as co-processing units for...
The High Efficiency Video Coding (HEVC) standard provides an outstanding compression performance and...
In this work, a highly parallel and flexible framework based on a multicore processor which is espec...
High Efficiency Video Coding (HEVC) doubles the coding efficiency of the prior Advanced Video Coding...
The High Efficiency Video Coding (HEVC) standard provides a higher compression efficiency than other...
The High Efficiency Video Coding (HEVC) standard provides higher compression efficiency than other v...
H.264/AVC is the latest standard for video compression and is a significant advance, but at the expe...
Heterogeneous systems on a single chip composed of CPU, Graphical Processing Unit (GPU), and Field P...
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that...
In the high efficiency video coding (HEVC) encoder, motion estimation (ME) takes up more than 50% en...
This paper provides a multiple-layer parallel motion estimation (ME) scheme implemented on GPU for H...
We propose a highly parallel and scalable motion estimation algorithm, named multilevel resolution m...
The new High Efficiency Video Coding (HEVC) standard will most likely be used in many applications i...
The high computational cost of the motion estimation module in the new HEVC standard raises the need...
Parallel processors such as Graphics processing units (GPUs) have emerged as co-processing units for...
Parallel processors such as Graphics processing units (GPUs) have emerged as co-processing units for...
The High Efficiency Video Coding (HEVC) standard provides an outstanding compression performance and...
In this work, a highly parallel and flexible framework based on a multicore processor which is espec...
High Efficiency Video Coding (HEVC) doubles the coding efficiency of the prior Advanced Video Coding...
The High Efficiency Video Coding (HEVC) standard provides a higher compression efficiency than other...
The High Efficiency Video Coding (HEVC) standard provides higher compression efficiency than other v...
H.264/AVC is the latest standard for video compression and is a significant advance, but at the expe...
Heterogeneous systems on a single chip composed of CPU, Graphical Processing Unit (GPU), and Field P...
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that...