1Citadel: Efficiently Protecting Stacked Memory From Large Granularity Failures

Abstract—Stacked memory modules are likely to be tightly integrated with the processor. It is vital that these modules operate reliably, where failure can require replacement of the entire socket. To make matters worse, stacked memory designs are susceptible to new failure modes (for example, due to faulty through-silicon vias, or TSVs) that can cause large portions of memory, such as a bank, to become faulty. To avoid data loss from large-granularity failures, the memory system may use symbol-based codes that stripe the data for a cache line across several banks (or channels). Unfortunately, such data-striping reduces memory-level parallelism, causing significant slowdown and higher memory power consumption. This paper proposes Citadel, a robust memory architecture that allows the memory system to store each cache line entirely within one bank, allowing high performance, low power and efficient protection from large-granularity failures. Citadel consists of three components; TSV-Swap, which can tolerate both faulty data-TSVs and faulty address-TSVs; Three Dimensional Parity (3DP), which can tolerate column failures, row failures, and bank failures; and Dynamic Dual-Granularity Sparing (DDS), which can mitigate permanent faults by dynamically replacing faulty memory regions with spares, either at a row granularity or at a bank granularity. Our evaluations with real-world DRAM failure data show that Citadel performs within 1 % of, and uses only an additional 4 % power versus a memory system optimized for performance and power, yet provides reliability that is 7x-700x higher than symbol-based ECC.