The priority division arbiter for low wcet and high resource utilization in multi-core architectures

Shared memory arbiters play a major role in determining the Worst Case Execution Time (Wcet) of applications executing on multi-core architectures. Apart from the produced Wcet, shared memory utilization is another important parameter which characterizes the suitability of an arbiter for a particular system. This paper compares the traditional arbiters, the Static priority (aka fixed priority), the Time Division Multiple Access (Tdma) and the Round robin against the Priority division arbiter on the above mentioned merits. The paper extends the Priority division arbiter by providing a new configuration, called h1, which is highly attractive for mixed critical systems with a single Hard Real-Time (Hrt) application. The paper derives formulas to calculate the worst case latency and the worst case memory utilization. The analysis proves that the Priority division arbiter outperforms the Tdma arbiter in memory utilization and the Round robin arbiter in the produced Wcet. Moreover, the Priority division arbiter, under the h1 mode, outperforms the Static priority arbiter in terms of the produced Wcet of the single Hrt application. The supporting evidences are achieved by conducting experiments on a quad-core NIOS architecture built on Altera Fpga. The test applications are chosen from the Mälardalen Wcet benchmark suit. 1