5th Americas International Conference on Production Research HILES DESIGNER: A MODELING TOOL FOR EMBEDDED SYSTEMS DESIGN VALIDATION

Verification and Validation (V&V) on embedded systems design is a crucial topic today. It is essential in systems design to create methods to measure the modeled behavior correctness in order to give more reliability to the design itself. Using formalisms such as Finite State Machine or Petri Nets, it is possible to verify formally or by simulation the design behavior. In this work, we present HiLeS Designer CAD tool to model and to verify systems formally and by simulation. This tool uses its own formalism that allows modeling heterogeneous systems in hierarchical levels, representing the logic behavior by Petri nets and the continuous behavior using VHDL-AMS. The Petri net part can be formally analyzed. The composed model can be transformed to a unique executable virtual prototype in VHDL-AMS. A remote keyless system is presented as an embedded system example. Keywords: Embedded system design, heterogeneous systems, Petri nets, validation, virtual prototype, VHDL-AMS