The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a graph model and the Gomory-Hu cut-equivalent tree algorithm, a bus can be partitioned into several bus segments separated by pass transistors. Highly communicating devices are placed to adjacent bus segments, so most data communication can be achieved by switching a small portion of the bus segments. Thus, a significant amount of power consumption can be saved. It can be proved that the proposed bus partitioning method achieves an optimal solution. The concept of tree clustering is also proposed ...
We propose a strategy to reduce the propagation delay of microprocessors’ digital bus lines at very ...
[[abstract]]The trend towards distributed, networked embedded systems is changing the way power shou...
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignmen...
Abstract — This paper1 proposes a bus-segmentation method that efficiently reduces the switched capa...
The segmented bus is a power-efficient architecture for intra-tile SoC communication, where energy i...
Abstract — The amount of energy consumed for interconnect-ing the IP-blocks is increasing significan...
Keywords—System-on-Chip, deep sub-micron technology, bus interconnection, segmented bus, power-aware...
The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we...
Shared-bus chip multiprocessors require buses with long wires. The portion of power consumed in wire...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
The communication and memory organization in system on chip are a major source of energy consumption...
Abstract — Sub-micron feature sizes have resulted in a considerable portion of power to be dissipate...
As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires ...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
System-on-chip (SoC) architectures have emerged as ubiquitous option for computation-intensive appli...
We propose a strategy to reduce the propagation delay of microprocessors’ digital bus lines at very ...
[[abstract]]The trend towards distributed, networked embedded systems is changing the way power shou...
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignmen...
Abstract — This paper1 proposes a bus-segmentation method that efficiently reduces the switched capa...
The segmented bus is a power-efficient architecture for intra-tile SoC communication, where energy i...
Abstract — The amount of energy consumed for interconnect-ing the IP-blocks is increasing significan...
Keywords—System-on-Chip, deep sub-micron technology, bus interconnection, segmented bus, power-aware...
The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we...
Shared-bus chip multiprocessors require buses with long wires. The portion of power consumed in wire...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
The communication and memory organization in system on chip are a major source of energy consumption...
Abstract — Sub-micron feature sizes have resulted in a considerable portion of power to be dissipate...
As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires ...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
System-on-chip (SoC) architectures have emerged as ubiquitous option for computation-intensive appli...
We propose a strategy to reduce the propagation delay of microprocessors’ digital bus lines at very ...
[[abstract]]The trend towards distributed, networked embedded systems is changing the way power shou...
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignmen...