We propose in this paper a novel approach for speeding timing clo-sure. We focus on the problem of accurate post-routing delay es-timation from a given placement. Post-routing delays differ from placement delays due to factors such as net topology, layer assign-ment and congestion. Fundamental to our approach is utilizing an existing base design to predict future designs. We present four wire-delay estimation techniques based on: delay fitting, Steiner-aware delay fitting, Steiner-aware RC sampling, and scaled Steiner-aware RC sampling. We apply our techniques to several designs, and using an industrial flow, we demonstrate that it is possible to estimate the routing delays with an average estimation error of 16% on benchmark circuits. Thes...
In link-state routing, routes are determined based on the estimates of the current delays on the lin...
To route and schedule trains over a large complex network can be computationally intensive. One way ...
Delay minimization methods are proposed for zero-skew routings. A delay-time estimation formula is d...
The inaccuracy of Elmore delay [3] for interconnect delay estimation is well-documented. However it ...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Experimental results show that our algorithm generates topologies with better delay compared to stat...
The main challenge for developing accurate and efficient delay metrics has been the prediction of d...
The multi-net Global Routing Problem (GRP) in VLSI physical design is a problem of routing a set of ...
Under manufacturing process variation, the circuit delay varies with process parameters. For delay t...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
This paper addresses the problem of true delay estimation during high level design. The true delay i...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
Computation of the second order delay in RC-tree based circuits is important during the design proce...
The design scale of Integrated Circuits (ICs) is increasing exponentially according to Moore's law, ...
In link-state routing, routes are determined based on the estimates of the current delays on the lin...
To route and schedule trains over a large complex network can be computationally intensive. One way ...
Delay minimization methods are proposed for zero-skew routings. A delay-time estimation formula is d...
The inaccuracy of Elmore delay [3] for interconnect delay estimation is well-documented. However it ...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
Experimental results show that our algorithm generates topologies with better delay compared to stat...
The main challenge for developing accurate and efficient delay metrics has been the prediction of d...
The multi-net Global Routing Problem (GRP) in VLSI physical design is a problem of routing a set of ...
Under manufacturing process variation, the circuit delay varies with process parameters. For delay t...
Abstract- This paper addresses the problem of true delay estimation during high level design. The ex...
This paper addresses the problem of true delay estimation during high level design. The true delay i...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
Computation of the second order delay in RC-tree based circuits is important during the design proce...
The design scale of Integrated Circuits (ICs) is increasing exponentially according to Moore's law, ...
In link-state routing, routes are determined based on the estimates of the current delays on the lin...
To route and schedule trains over a large complex network can be computationally intensive. One way ...
Delay minimization methods are proposed for zero-skew routings. A delay-time estimation formula is d...