Checking Pipelined Distributed Global Properties for Post-silicon Debug

Abstract— While multi-processor system-on-chips (MPSOCs) with network-on-chip (NOC) interconnect are becoming increasingly common to meet the constant performance demand, it is due to communication delays in the NOC extremely complicated to ensure that software executes correctly. In this paper, we extend our architecture that non-intrusively observes global properties at run time using distributed monitors such that not only single tokens but also pipelined tokens can be monitored. We detail the solution for a given race and compare the alternatives of having one large monitor versus multiple small monitors. Index Terms—Validation, races, monitors, distributed property checking I