Throughput analysis and voltage-frequency island partitioning for streaming applications under process variation

Abstract—Variability in the manufacturing process results in variation in the maximum supported frequency of individual cores in a Multi-Processor System-on-Chip (MPSoC). This vari-ation needs to be considered when performing statistical timing analysis in the system-level design. As our first contribution, we present a framework to estimate the probability distribution of application throughput (e.g. frames per second in video decoding) in a system with Voltage-Frequency Island (VFI) partitions in the presence of process variation. The novelty of the framework lies in the computation of the probability distribution of throughput, based on a user-specified set of clock-frequency levels per VFI domain considering both within-die and die-to-die variations of cores. As a second contribution, we provide a methodology to perform variation-aware partitioning of the cores of an MPSoC into VFIs for maximized timing yield (percentage of chips that satisfy a given throughput requirement). On a case study, we demonstrate how our methodology can be used by system designers for two purposes: 1) to make trade-offs between the number of VFI partitions (design cost) and timing yield; 2) to estimate the impact of reducing circuit design margins on the number of good dies on a wafer. We illustrate that the proposed variation-aware partitioning provides up to 18 % improvements in the timing yield compared to a deterministic partitioning. I