9.2 A Low-Power Multi-Bit! " Modulator in 90nm Digital CMOS without DEM

There is an increasing demand for low-power, high-signal-band-width SoCs. The challenges faced by delta-sigma (!") modulators used in these applications are two folds: they must provide large dynamic range and they must coexist with the digital core in a digital CMOS process. This second-order multi-bit delta-sigma modulator (!"M) uses a 4b ADC. The truncation of the digital ADC output, the shaping of the error, and its cancellation, enable using a 3-level DAC in the main feedback loop and a 5-level DAC in the second integrator feedback loop. This design uses fCLK=40MHz. The circuit achieves 51dB SNDR with OSR=10 and 72dB SNDR with OSR=50. Accordingly, the architecture meets the requirements of many applications including wireless base-band systems [1], [2]. The use of a second-order modulator reduces the digital filter complexity. Moreover, a second-order loop is good for low power.