A Scalable GPU Architecture based on Dynamically Reconfigurable Embedded Processor

The increasing cost of ASIC has been driving designers to choose more flexible solutions, as new chip architectures should deliver high performance while maintaining low power consumption, area, and costs in shorter time-to-market environments. As a result, reconfigurable processors (RPs) have become increasingly important in recent years. ex) Reconfigurable Processor (RP) for multi-media applications: H.264/AVC [1,2], Video [3], Audio [4], Graphics [5] In this work, we present a new approach that utilizes an RP to design a tile based GPU, a core component of today’s mobile application processors. Experimental results show that the use of RP based GPUs can be a versatile graphics solution, as they support scalable, flexible architecture models. The Samsung Reconfigurable Processor(SRP) is a proprietary low-power DSP core developed by Samsung Electronics Ltd., as an elaboration on ADRES [6]. The SRP is a flexible architecture template that allows a designer to easily generate different instances by specifying different configurations in the target architecture. The SRP includes a tightly coupled VLIW engine and a coarse grained reconfigurable array (CGRA). The VLIW engine is useful for general purpose computations such as function invocation and branch selection. The CGRA makes full use of the software pipeline technique via modulo scheduling [7] to allow loop acceleration. Consequently, the CGRA exhibits a high IPC rate, up to the maximum number of FU arrays. During the execution phase, a central pointer allows dynamic reconfiguration of the FUs within a given cycle. The integration of VLIW and CGRA allows the SRP to more effectively exploit instruction- and loop-level parallelism