A Comparative Review and Evaluation of Approximate Adders

As an important arithmetic module, the adder plays a key role in determining the speed and power consumption of a digital signal processing (DSP) system. The demands of high speed and power eciency as well as the fault tolerance nature of some applications have promoted the development of approximate adders. This paper reviews current approx-imate adder designs and provides a comparative evaluation in terms of both error and circuit characteristics. Simula-tion results show that the equal segmentation adder (ESA) is the most hardware-ecient design, but it has the lowest accuracy in terms of error rate (ER) and mean relative error distance (MRED). The error-tolerant adder type II (ETAII), the speculative carry select adder (SCSA) and the accuracy-con gurable approximate adder (ACAA) are equally accu-rate (provided that the same parameters are used), how-ever ETATII incurs the lowest power-delay-product (PDP) among them. The almost correct adder (ACA) is the most power consuming scheme with a moderate accuracy. The lower-part-OR adder (LOA) is the slowest, but it is highly ecient in power dissipation