Fractional-N PLL with 90º Phase Shift Lock and Active Switched-Capacitor Loop Filter

Abstract-This paper describes a new possibility of fully integrated fractional-N phase locked loop (PLL). The approach uses switched-capacitor fully differential low pass filter (LPF) instead of huge continuous-time filter. The discrete-time operation has the potential to provide a phase noise enhancement (PNE) block, variable gain, to improve noise. The circuit is implemented in 2.8 mm2 including all capacitors and Ȉǻ modulator using 0.25 µm CMOS process. The proposed PLL achieves a phase noise of-102 dBc at 600 kHz and spur level of-80 dBc with mid-band frequency. Power dissipation is 30 mW with a 3-V supply. I