A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Abstract. Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. In this paper, we propose to augment a processor, realized in CMOS, with custom instruction set extensions, realized in a protected logic, having both security and performance as the primary objectives. We have devel-oped a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid implementations. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher be-tween protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.