VLSI Hardware Implementation For Soft-Decision Minimum Weight Decoder

A soft-decision decoder is much more complex than a hard-decision decoder. Soft-decision minimum weight decoding is near maximum likelihood decoding algorithm. It is a modified error trapping technique for cyclic block codes. In this paper a VLSI chip design implementation for a soft-decision minimum weight decoder is presented. The binary (7, 4) Hamming codes are presented as an example, to show that the decoder can detect and correct the introduced error. VHDL (VHSIC Hardware Description Language) is used for describing the design, by writing VHDL source code program. An FPGA (Field Programmable Gate Array) is the target technology of the design. 1