A novel trace- pipelined binary arithmetic coder architecture for JPEG 2000

Embedded block coding with optimized truncation (EBCOT) employed in the JPEG2000 standard accounts for the majority of the processing time, because the EBCOT is full of bit operations that cannot be implemented efficiently in software. The block coder consists of a bit-plane coder (BPC) followed by a binary arithmetic coder (BAC), where the most up-to-date BPC architectures are capable of producing symbols at a much higher rate than the conventional BACs can handle. This paper proposes a novel pipelined BAC architecture that can encode input symbols at a much higher rate than the conventional BAC architectures. The proposed architecture can significantly reduce the critical path delay and can achieve a throughput of 400 M symbols/sec. The critical path delay synthesized with 0.18-ૄm CMOS technology is 2.42 ns, which is almost half of the delay taken in conventional BAC architectures. Index Terms—EBCOT, JPEG2000, VLSI architecture, arithmetic coding, trace schedulin