Add to ORKGAbstract — An ultra low-power SAR ADC is presented. The circuit is the interleaved version of an already designed SAR converter with improved performance. This design uses 7 interleaved converters and achieves a conversion rate of 700 kS/s. The converter has been simulated by using a 0.18-µm CMOS technology showing a power consumption as low as 40 µW which allows obtaining a state-of-the-art FoM equal to 37 fJ/conv.-step. The architectural study together with converter simulation results are presented. I
An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sam...
Power consumption is one of the main design constraints in today’s integrated circuits. For systems ...
With the growing market of MCUs and embedded electronic powered by batteries, more energy efficient ...
This thesis presents an improved ultra-low power 10-bit 1 kS/s successive approximation (SAR) analog...
A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power ...
High-speed low-power analog-to-digital converters (ADCs) find application in communication systems a...
This master?s thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS...
This work investigates power-efficient correction methods for ultra low-power time-interleaved SAR c...
In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to...
A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step...
This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good p...
Many wireline communication systems are moving toward a digital based architecture for the receiver ...
This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-po...
Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-effici...
This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMO...
An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sam...
Power consumption is one of the main design constraints in today’s integrated circuits. For systems ...
With the growing market of MCUs and embedded electronic powered by batteries, more energy efficient ...
This thesis presents an improved ultra-low power 10-bit 1 kS/s successive approximation (SAR) analog...
A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power ...
High-speed low-power analog-to-digital converters (ADCs) find application in communication systems a...
This master?s thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS...
This work investigates power-efficient correction methods for ultra low-power time-interleaved SAR c...
In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to...
A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step...
This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good p...
Many wireline communication systems are moving toward a digital based architecture for the receiver ...
This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-po...
Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-effici...
This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMO...
An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sam...
Power consumption is one of the main design constraints in today’s integrated circuits. For systems ...
With the growing market of MCUs and embedded electronic powered by batteries, more energy efficient ...