Area-Time Efficient Multi-Moduli Adder Design

Abstract—Multi-moduli architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable digital processors and fault-tolerant systems that are based on the Residue Number System (RNS). Two novel architectures are proposed for multi-moduli adders that support the most common moduli cases in RNS channels, that is, modulo 2n 1; 2n and 2n + 1. The proposed architectures use parallel prefix carry computation units composed of log2 n levels. The experimental results show that the resulting adders are significantly faster and / or area efficient than the earlier proposals. Index Terms—Multi-moduli architectures, residue number sys-tem, modulo 2n1 arithmetic, parallel prefix carry computation I