On Design of a Fault Tolerant Reversible 4-Bit Binary Counter with Parallel Load

Abstract: Reversible logic is one of the ways for power optimization. The produced circuits using these gates are applied in nanotechnology, bioinformatics, quantum computing and DNA. In this paper, we propose a fault tolerant reversible 4-Bit binary counter with parallel load. This is a robust and first attempt for designing a fault tolerant reversible 4-Bit binary counter with parallel load. Counters are important components in computers. Most counters are synchronous in computer systems. Some of these counters can also be made from D-Flip Flops. Counters can be designed to generate any desired sequence of states. The sequence may follow the binary count or may be any other arbitrary sequence. In this study, we propose three approaches of the fault tolerant reversible circuits for 4-Bit binary counter with parallel load. Total logical calculation and Total quantum cost of the second approach is less than the previous approaches. Third approach is implemented using Unit 3 gate. The constant inputs and the garbage outputs of its circuit is less than the mentioned approaches. All the scales are in the nanometric area. The proposed circuits can be applied for constructing more complex systems in nanotechnology