FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm

Abstract—Competitive majority network trained by error cor-rection (C-Mantec), a recently proposed constructive neural net-work algorithm that generates very compact architectures with good generalization capabilities, is implemented in a field program-mable gate array (FPGA). A clear difference with most of the existing neural network implementations (most of them based on the use of the backpropagation algorithm) is that the C-Mantec automatically generates an adequate neural architecture while the training of the data is performed. All the steps involved in the implementation, including the on-chip learning phase, are fully described and a deep analysis of the results is carried on using the two sets of benchmark problems. The results show a clear increase in the computation speed in comparison to the standard personal computer (PC)-based implementation, demonstrating the usefulness of the intrinsic parallelism of FPGAs in the neurocom-putational tasks and the suitability of the hardware version of the C-Mantec algorithm for its application to real-world problems. Index Terms—Circuit complexity, constructive neural networks (CoNN), on-chip learning, threshold networks. I