A Contribution Towards Architectures and Algorithms for Self Repair of RAMs

Built-in self repair (BISR) for RAMs is an established and widely used approach to increase system-on-chip (SoC) yield. One key BISR component is the repair analysis al-gorithm (RA) used to replace faulty memory cells with redundant ones. Many RAs were proposed during the past three decades mainly for traditional memories but recently some for block-based memories as well. How-ever, existing RAs for block-based memories suffer from lower repair effectiveness than some of the algorithms for traditional memories. Moreover, none of them guarantees finding an optimal memory repair solution. In this work, a new RA for block-based bit-oriented RAMs is proposed and verified by software simulations. The experimental results indicate that the new algorithm is suitable for use in SoCs. For certain memory parameters (size, the numbers of spares and quadrants, fault distri-bution), it is more effective than the most effective known RA for such memories by up to 4 %. Furthermore, the additional on-chip algorithm area is within acceptable lev-els in comparison to similar RA for traditional memories. For certain memory parameters (the numbers of spares and quadrants) the additional area fluctuates from-5 % to +3 %. The new algorithm also guarantees finding an optimal memory repair solution