SynFull: Synthetic traffic models capturing a full range of cache coherence behaviour

Modern and future many-core systems represent complex ar-chitectures. The communication fabrics of these large systems heavily influence their performance and power consumption. Current simulation methodologies for evaluating networks-on-chip (NoCs) are not keeping pace with the increased com-plexity of our systems; architects often want to explore many different design knobs quickly. Methodologies that capture workload trends with faster simulation times are highly ben-eficial at early stages of architectural exploration. We pro-pose SynFull, a synthetic traffic generation methodology that captures both application and cache coherence behaviour to rapidly evaluate NoCs. SynFull allows designers to quickly indulge in detailed performance simulations without the cost of long-running full-system simulation. By capturing a full range of application and coherence behaviour, architects can avoid the over or underdesign of the network as may occur when using traditional synthetic traffic patterns such as uni-form random. SynFull has errors as low as 0.3 % and provides 50 × speedup on average over full-system simulation. 1