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Error-correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. Error detection is the detection of errors caused by noise or other impairments during transmission from the transmitter to the receiver. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. The Bose, Ray- Chaudhuri, Hocquenghem (BCH) codes are one of the powerful error-correcting codes. This paper describes the design and simulation of (255, 215, 5) BCH Encoder and Syndrome Calculation circuitry using VHDL for reliable data transfer in AWGN channel with error correcting capability of ‘t’=5. The digital logic implementation of binary encoding of BCH (255, 215, 5) of length n=255 over GF (28) with primitive polynomial 1+x+x2+x7+x8 is organized into Linear Feedback Shift Registers (LFSR). The proposed syndrome block is used to optimize the hardware consumption required for the design and implementation